Embodiments of the present invention relate to cache memory devices. In particular, the present invention relates to a method and apparatus for sharing of a cache memory device by multiple computing engines.
Computer systems may contain multiple computing engines. For example, an integrated circuit chip may include a Central Processing Unit (CPU) and a graphics processor. The computing engines in a system may share system resources. In the example above, the CPU and the graphics processor may share a system memory device, such as a Random Access Memory (RAM) device. The second computing engine may only need the shared resource at certain times, and thus the resource may be shared dynamically. For example, at some times the CPU may have access to the entire system memory, and at other times (e.g., when the graphics processor is performing a graphics operation), the CPU may share the system memory with the graphics processor. In this example, the system memory may switch during the course of system operation between shared mode and non-shared mode depending on the needs of the graphics processor.
The information (e.g., data and instructions) that a computing engine stores in a RAM may be cached in a cache memory device (xe2x80x9ccachexe2x80x9d), such as a Static Random Access Memory (SRAM). A cache may have single ported arrays, in which case each bit storage cell in an array only has a single output and single output port (i.e., a single sense amp), or may be multi-ported, in which case each cell in the array has multiple ports. Cache sharing is a technique by which a cache is shared between multiple computing engines, such as a CPU and a graphics processor. In some systems, the cache farthest from the processor core is shared.
One approach to cache sharing is for both computing engines to send requests through the bus controller, such as the CPU""s bus controller. This approach requires that the bus be shared, which may possibly affect CPU performance. In addition, this approach is generally inadequate to support multiple simultaneous cache accesses, particularly where the cache is single ported.